Applies Universal Verification Methodology (UVM) best practices and testing patterns to systematically validate and verify complex hardware design workflows in Claude Code.

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fpga-debugging🎯Skill

Assists developers in systematically diagnosing and resolving hardware design issues in FPGA projects by providing structured debugging workflows and automated analysis techniques.

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cdc-analysis🎯Skill

Analyzes Change Data Capture (CDC) logs to detect and validate data transformations, schema changes, and potential synchronization issues across database systems.

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timing-constraints🎯Skill

Manages and enforces precise time-based scheduling and duration limits for workflow steps in Claude Code development processes.

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hdl-simulation🎯Skill

hdl-simulation skill from a5c-ai/babysitter

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sva-assertions🎯Skill

Validates system-level assertions and generates formal verification reports for code quality and correctness during complex development workflows.