Collection18 items

a5c-ai/babysitter

9stars

🎯Skills17

Scaffolds new babysitter process definitions by guiding users through a structured 3-phase workflow from research to implementation.

process-builder

🎯fsm-design🎯Skill

Generates finite state machine (FSM) designs by creating structured state transition diagrams and corresponding implementation code based on specified workflow requirements.

fsm-design

🎯axi-protocol🎯Skill

Translates and validates AXI (Advanced eXtensible Interface) protocol communication specifications for hardware design and verification workflows.

axi-protocol

🎯timing-constraints🎯Skill

Manages and enforces precise time-based rules and deadlines for workflow steps, ensuring tasks are completed within specified time windows or intervals.

timing-constraints

🎯fpga-debugging🎯Skill

Assists developers in systematically diagnosing and resolving hardware design issues in FPGA projects by providing structured debugging workflows and automated error analysis.

fpga-debugging

🎯vhdl-language🎯Skill

Skill

vhdl-language

🎯sva-assertions🎯Skill

Validates and enforces system-level assertions for software verification and automated quality control within complex multi-step workflows.

sva-assertions

🎯synthesis-optimization🎯Skill

Optimizes and refines code generation workflows by iteratively improving synthesis processes, ensuring higher quality code outputs through systematic refinement and quality convergence techniques.

synthesis-optimization

🎯content-optimization🎯Skill

Optimizes and refines content by iteratively improving text quality, structure, and clarity through AI-driven analysis and targeted revisions.

content-optimization

🎯ip-core-management🎯Skill

Manages intellectual property (IP) core configurations, tracking, and governance within software development workflows, ensuring compliance and standardized IP asset management.

ip-core-management

🎯hdl-simulation🎯Skill

Simulates and validates hardware description language (HDL) designs by running iterative tests and quality checks on digital circuit models.

hdl-simulation

🎯verilog-sv-language🎯Skill

Provides intelligent code generation, analysis, and refactoring capabilities specifically for Verilog and SystemVerilog hardware description languages.

verilog-sv-language

🎯power-analysis🎯Skill

Analyzes computational resource requirements, performance bottlenecks, and energy consumption patterns for complex multi-step workflows in the Babysitter orchestration framework.

power-analysis

🎯cdc-analysis🎯Skill

Analyzes Change Data Capture (CDC) events and workflows to validate data integrity, detect anomalies, and ensure consistent event processing across distributed systems.

cdc-analysis

🎯formal-verification🎯Skill

Validates and proves the correctness of code or system specifications using mathematical and logical methods to ensure safety, reliability, and absence of critical errors.

formal-verification

🎯rtl-linting🎯Skill

Performs real-time linting for RTL (Right-to-Left) language code and layout, ensuring proper text directionality, alignment, and language-specific coding standards.

rtl-linting

🎯place-and-route🎯Skill

Skill

place-and-route

🏪Marketplaces1

🏪a5c-ai-babysitter🏪Marketplace

Babysitter enables Claude Code to manage sophisticated development workflows through deterministic, resumable orchestration

communitybabysitterplugins:1

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